A Built-In IDDQ Testing Circuit*
نویسندگان
چکیده
Although IDDQ testing has become a widely accepted defect detection technique for CMOS ICs, its effectiveness in very deep submicron technologies is threatened by the increased transistor leakage current. In this paper, a built-in IDDQ testing circuit is presented, that aims to extend the viability of IDDQ testing in future technologies and first experimental results are discussed.
منابع مشابه
An Embedded IDDQ Testing Architecture and Technique
In this paper an embedded IDDQ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing applications. Moreover, a technique that utilises the IEEE 1149.1 boundary scan standard to control the proposed architecture is provided. The proposed solution is characterised by low silicon area requirements and permi...
متن کاملFuzzy-based Circuit Partitioning in Built-in Current Testing Fuzzy rules and fuzzy sets
Partitioning a digital circuit into modules before implementing on a single chip is key to balancing between test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistic analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible since IDDQ testing requires the measurement of an analog quan...
متن کاملFuzzy-based circuit partitioning in built-in current testing
Partitioning a digital circuit into modules before implementing on a single chip is key to balancing between test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistic analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible since IDDQ testing requires the measurement of an analog quan...
متن کاملTesting DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results
This paper presents the implementation and results of the test suite for DSM ASIC consisting of static, ∆Iddq, and dynamic patterns based on scan, and quantitatively reports the advantages of dynamic pattern over AC static pattern, even at a low frequency, and advantages of ∆Iddq test over traditional Iddq. A defect level calculation method is presented which decomposes the defect level into, a...
متن کاملA Novel Iddq Scanning Technique For Pre-Bond Testing
Electronic Stacked integrated circuits presents many advantages like short latency, low power consumption, and immense amount of bandwidth delivered by Through Silicon Vias (TSV). However, these circuits present many test issues, designer must ensure that each of individual die layer is designed to be testable before bonding take places. In this paper we propose a novel technique of Design for ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2005